ECL/PECL/HSTL Clock Driver, 2.5/3.3 V, LQFP-32

The MC100LVEP111 is a low skew 2:1:10 differential driver,
designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or
single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP111 is operating under PECL conditions.

To ensure the tightest skew, both sides of the differential outputs identically terminate
into 50 ohms, even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew.