PIC-AVR® microcontroller, 32-bit, 1.8-3.3V, 256 KB, 66 MHz, LQFP

32-bit Atmel AVR microcontroller
AT32UC3A0512, AT32UC3A0256, AT32UC3A0128
AT32UC3A1512, AT32UC3A1256, AT32UC3A1128

Features
- 32-bit Atmel® AVR® microcontroller with high performance and low power consumption
- Compact single-cycle RISC instruction set including DSP instruction set
- Read-modify-write instructions and atomic bit manipulation
- Performance 1.49 DMIPS / MHz
- Up to 91 DMIPS running at 66 MHz from flash (1 wait state)
- Up to 49 DMIPS running at 33MHz from flash (0 wait state)
- Memory protection unit
- Multi-hierarchy bus system
- Powerful data transfers on separate buses for increased performance
- 15 peripheral DMA channels improve speed for peripheral communication
- Internal high-speed flash
- 512K bytes, 256K bytes, 128K bytes versions
- Single-cycle access up to 33 MHz
- Prefetch buffer to optimize instruction execution at maximum speed
- 4 ms page programming time and 8 ms full-chip erase time
- 100,000 write cycles, 15-year data retention capability
- Flash security locks and user-defined configuration area
- Internal high-speed SRAM, single-cycle access at full speed
- 64K bytes (512KB and 256KB Flash), 32K bytes (128KB Flash)
- External memory interface on AT32UC3A0 derivatives
- SDRAM / SRAM compatible memory bus (16-bit data and 24-bit address buses)
- interrupt controller
- Autovectored Low Latency Interrupt Service with Programmable Priority (Autovectored Low Latency Interrupt Service with Programmable Priority)
- System functions
- Power and clock manager including internal RC clock and a 32KHz oscillator
- Two general purpose oscillators and two phase-locked loops (PLL) enable
Independent CPU frequency from USB frequency
- Watchdog timer, real-time clock timer
- Universal serial bus (USB)
- Device 2.0 Full speed and On-The-Go (OTG) Low speed and full speed
- Flexible endpoint configuration and management with dedicated DMA channels
- On-chip transceiver including pull-ups
- Ethernet MAC 10/100 Mbps interface
- 802.3 Ethernet media access controller
- Supports Media Independent Interface (MII) and Reduced MII (RMII)
- One three-channel 16-bit timer/counter (TC)
- Three external clock inputs, PWM, capture and various counting functions
- One 7-channel 16-bit pulse width modulation (PWM) controller
- Four universal synchronous/asynchronous receivers/transmitters (USART)
- Independent baud rate generator, support for SPI, IrDA and ISO7816 interfaces
- Support for hardware handshaking, RS485 interfaces and modem line
- Two serial master/slave peripheral interfaces (SPI) with chip selection signals
- One controller for synchronous-serial protocol
- Supports I2S and generic frame-based protocols
- A master/slave two-wire interface (TWI), 400kbit/s I2C compatible
- An 8-channel 10-bit analog-to-digital converter
- 16-bit stereo audio bitstream - sampling rate up to 50 KHz
- On-chip debug system (JTAG interface)
- Nexus class 2+, runtime control, non-intrusive data and program tracking
- 100-pin TQFP (69 GPIO pins), 144-pin LQFP (109 GPIO pins)
- 5V input tolerant I/Os
- Single 3.3V power supply or dual 1.8V-3.3V power supply

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